1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device which includes a step of removing an oxide layer on a planarized material layer and a step of re-depositing another material layer using the same process tool.
2. Description of the Prior Art
Poly-silicon has been conventionally used as a gate electrode in semiconductor devices, such as metal-oxide-semiconductors (MOS). With the trend towards scaling down semiconductor devices, however, conventional poly-silicon gates have inferior performances due to boron penetration and an unavoidable depletion effect, which increases the equivalent thickness of the gate dielectric layer, reduces the gate capacitance, and lowers a driving force of the devices. Therefore, work function metals are used to replace the conventional poly-silicon gate (which acts as a sacrificial gate) as a metal gate that is suitable for a high-k gate dielectric layer.
A poly-silicon material layer is formed on the substrate including fin structures to serve as a sacrificial gate for the later performed replacement metal gate (RMG) process, the protruded fin structures may cause non-planar surface of the poly-silicon material layer. Therefore, a chemical mechanical polishing (CMP) process needs to be performed to planarize the poly-silicon material layer to improve the reliability of the later formed semiconductor devices. Because there is no etch stop layer, the CMP process is usually modulated by a time mode. However, the process deviation, such as too long processing time or improper concentration of the slurry, of the CMP process causes the formed poly-silicon material layer to fail to meet predetermined criteria; for example, the formed poly-silicon material layer has a thickness less than a target thickness, which may further cause some wafers to be scraped to increase the manufacturing cost.
Accordingly, a method of fabricating a semiconductor device—more specifically a sacrificial gate process—that can compensate the deficiency of the sacrificial gate material layer such as the insufficient thickness after the CMP process and avoid unwanted wafer scraps to thereby reduce the manufacturing cost and improve the performance of the semiconductor device is needed in the industry.